1. Field of the Invention
Generally, the present disclosure relates to the fabrication of integrated circuits, and, more particularly, to transistors comprising a high-k metal gate electrode formed in an early manufacturing stage.
2. Description of the Related Art
The fabrication of complex integrated circuits requires the provision of a large number of transistor elements, which represent the dominant circuit element in complex integrated circuits. For example, several hundred millions of transistors may be provided in presently available complex integrated circuits. Generally, a plurality of process technologies are currently practiced, wherein, for complex circuitry, such as microprocessors, storage chips and the like, CMOS technology is currently the most promising approach due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. In CMOS circuits, complementary transistors, i.e., P-channel transistors and N-channel transistors, are used for forming circuit elements, such as inverters and other logic gates to design highly complex circuit assemblies, such as CPUs, storage chips and the like. A MOS transistor or generally a field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, comprises so-called PN junctions that are formed by an interface of highly doped drain and source regions and an inversely or weakly doped channel region disposed between the drain region and the source region. The conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed in the vicinity of the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, on the distance between the source and drain regions, which is also referred to as the channel length. Thus, the reduction of the channel length, and associated therewith the reduction of the channel resistivity, is a dominant design criterion for accomplishing an increase in the operating speed of the integrated circuits.
The continuing shrinkage of the transistor dimensions, however, involves a plurality of issues associated therewith that have to be addressed so as to not unduly offset the advantages obtained by steadily decreasing the channel length of MOS transistors. For example, highly sophisticated dopant profiles, in the vertical direction as well as in the lateral direction, are required in the drain and source regions so as to provide low sheet and contact resistivity in combination with desired channel controllability.
With a reduced channel length, generally a shallow dopant profile may be required in the drain and source regions, while nevertheless a moderately high dopant concentration is necessary in view of providing a low series resistance, which in turn results in a desired drive current in combination with a reduced transistor channel. A shallow dopant profile in combination with a low overall drain and source resistance is typically realized by forming so-called drain and source extension regions, which may represent extremely shallow doped areas extending below the gate electrode structure so as to appropriately connect to the channel region. On the other hand, an increased lateral offset from the channel region is adjusted on the basis of appropriately dimensioned sidewall spacers, which are used as implantation masks for forming the actual drain and source regions with a desired high dopant concentration and with an increased depth compared to the drain and source extension regions. By appropriately selecting the size of the drain and source extension regions, channel controllability may be maintained for very short channel transistors, while also providing a desired low overall series resistance in connecting the drain and source regions to the channel region. Consequently, for a desired performance of sophisticated transistor elements, a certain degree of overlap of the drain and source extension regions with the gate electrode is desirable in order to obtain a low threshold voltage and a high current drive capability. The overlap of the drain and source extension regions with the gate electrode gives rise to a specific capacitive coupling that is also referred to as Miller capacitance. Typically, a desired Miller capacitance is adjusted on the basis of implantation processes in which the drain and source dopants may be introduced in order to form the basic configuration of the drain and source extension regions, wherein the final shape of these regions may then be adjusted on the basis of a sequence of anneal processes in which implantation-induced damage is re-crystallized and also a certain degree of dopant diffusion may occur, thereby finally determining the resulting Miller capacitance.
Upon continuously reducing the channel length of field effect transistors, generally an increased degree of capacitive coupling is required in order to maintain controllability of the channel region, which may typically require an adaptation of a thickness and/or material composition of the gate dielectric material. For example, for a gate length of approximately 80 nm, a gate dielectric material based on silicon dioxide with a thickness of less than 2 nm may be required in high performance transistors, which may, however, result in increased leakage currents caused by hot carrier injection and direct tunneling of charge carriers through the extremely thin gate dielectric material. Since a further reduction in thickness of silicon dioxide-based gate dielectric materials may increasingly become incompatible with thermal power requirements of sophisticated integrated circuits, in particular for devices designed for low power applications, such as mobile devices and the like, other alternatives have been developed in increasing the charge carrier mobility in the channel region, thereby also enhancing overall performance of field effect transistors. One promising approach in this respect is the generation of a certain type of strain in the channel region, since the charge carrier mobility in silicon strongly depends on the strain conditions of the crystalline material. For example, for a standard crystallographic configuration of the silicon-based channel region, a compressive strain component in a P-channel transistor may result in a superior mobility of holes, thereby increasing switching speed and drive current of P-channel transistors.
One efficient mechanism for inducing a desired strain in the channel region of transistors is the deposition of a highly stressed material in close proximity to the transistors. To this end, frequently, in the contact level of the device, i.e., the interlayer dielectric material passivating the transistors and separating the transistors from the metallization system, appropriate materials may be provided, for instance in the form of a highly stressed silicon nitride material and the like, so that the internal stress may efficiently act on the channel region of the underlying transistors. In sophisticated device geometries, however, generally the deposition of an interlayer dielectric material in a void-free manner is difficult to achieve since the lateral distance between closely spaced gate electrode structures is in the range of 150 nm and significantly less. In particular, in combination with the above-described strain-inducing mechanism, deposition-related irregularities, such as voids, are frequently produced upon forming the highly stressed dielectric material since, in this case, the deposition conditions are significantly determined by the requirement of inducing a high internal stress level upon depositing the dielectric material.
Furthermore, in view of reducing static and dynamic leakage currents for low power applications, such as mobile devices and the like, an appropriate adaptation of the material composition of the gate dielectric material has been contemplated so that, for a physically appropriate thickness of a gate dielectric material, i.e., for obtaining an acceptable level of gate leakage currents, nevertheless, a desired high capacitive coupling is achieved. To this end, material systems have been developed, which have a significantly higher dielectric constant compared to the conventionally used silicon dioxide-based materials, such as silicon oxynitride and the like. For example, dielectric material including hathium, zirconium, aluminum and the like have a significantly higher dielectric constant and are, therefore, referred to as high-k dielectric materials, which are to be understood as materials having a dielectric constant of 10.0 and higher. Frequently, these high-k dielectric materials are provided in an early manufacturing stage, i.e., upon forming the gate electrode structures, possibly in combination with additional metal-containing electrode materials, which are used to appropriately adjust the work function and thus the threshold voltage of the transistors. Since these materials may sensitively respond to a plurality of reactive process atmospheres encountered during the further processing of the devices, an encapsulation of these materials may have to be ensured, which is typically accomplished by forming an appropriate silicon nitride spacer element on sidewalls of the sensitive gate materials immediately after patterning the complex gate layer stack.
Basically, the above-described process sequence allows providing potentially sophisticated semiconductor devices designed for low power applications, while nevertheless the individual transistor elements exhibit a more or less high performance, for instance due to the overall reduced size in combination with, for instance, moderately low gate leakage currents achieved by the provision of a high-k dielectric material. It turns out, however, that significant yield loss may be observed in semiconductor devices formed on the basis of the above-described process flow, while additionally overall performance is lower than expected, although sophisticated transistor designs and material compositions in the gate electrode structures may be used.
With reference to FIGS. 1a and 1b, a typical complex manufacturing flow for forming semiconductor devices on the basis of reduced critical dimensions, for instance with gate lengths of 40 nm and less, will be described in more detail.
FIG. 1a schematically illustrates a cross-sectional view of a semiconductor device 100 in a very advanced manufacturing stage. As shown, the device 100 comprises a substrate 101 and a semiconductor layer 102, which may in combination form a silicon-on-insulator (SOI) architecture when a buried insulating material (not shown) is formed below the semiconductor layer 102. In other cases, a bulk configuration is used in which the semiconductor layer 102 is in direct contact with a crystalline semiconductor material of the substrate 101. The semiconductor layer 102 comprises a plurality of active regions which are to be understood as semiconductor regions that are laterally delineated by appropriate isolation structures 102C and in and above which one or more transistors are formed. For convenience, in FIG. 1a, an active region 102A is illustrated so as to comprise transistors 150A, 150B. The transistors 150A, 150B may represent P-channel transistors or N-channel transistors and comprise drain and source regions 152, which are formed on the basis of drain and source extension regions 152E and deep drain and source areas 152D. Furthermore, in order to improve the overall series resistance, a metal silicide material 153 is typically provided in the drain and source regions 152. Moreover, the transistors 150A, 150B comprise respective gate electrode structures 160, which in turn include a gate dielectric material 161 which typically includes, as discussed above, a high-k dielectric material, such as hafnium oxide and the like. It should be appreciated that also conventional dielectric components or species, such as silicon oxide-based materials, silicon oxynitride and the like, may be implemented in the gate insulation layer 161 in order to provide stable interface characteristics and the like. Moreover, an electrode material 162, which may comprise specific work function metal species or other metal-containing electrode materials, such as titanium nitride, tantalum, tantalum nitride and the like, is formed on the gate dielectric material 161 and may also comprise a significant amount of a semiconductor material, such as silicon. Moreover, in the manufacturing stage shown, a metal silicide 163 is provided so as to enhance the electronic characteristics of the gate electrode structures 160. Furthermore, as discussed above, a sidewall spacer 164 is formed so as to laterally enclose sensitive gate materials, such as the gate dielectric material 161 and also the electrode material 162. To this end, a dense silicon nitride material is frequently used. Furthermore, a spacer 165, for instance comprised of silicon dioxide, is provided and typically has a width that is appropriate for incorporating the drain and source dopant species for the extension regions 152E. Furthermore, a further spacer 166, such as a silicon nitride spacer, is provided and may have, in the manufacturing stage shown, a reduced width in order to increase a lateral distance 150X between the gate electrode structures 160 prior to the further processing.
The semiconductor device 100 as shown in FIG. 1a may be formed on the basis of the following process strategy. The active region 102A is typically provided by forming isolation regions 102C, such as trench isolations, using well-established and complex lithography, etch, deposition and planarization techniques. Thereafter, appropriate materials for the gate dielectric layer 161 and the electrode material 162 are provided in combination with hard mask materials, for instance in the form of silicon nitride and the like. It should be appreciated that, if required, prior to providing a semiconductor-based electrode material, patterning processes may be applied in combination with appropriate deposition processes in order to provide work function metal species that comply with the requirements of P-channel transistors and N-channel transistors, respectively. After the complex process for patterning the materials 161 and 162, the liner material for the spacer element 164 is deposited, possibly in combination with the material of the spacer 165 and is thus patterned on the basis of, for instance, anisotropic etch strategies, followed by the patterning of the spacer 165. Consequently, these patterning processes cause a significant loss of material of the active region 102A thereby contributing to a significant recessing, as indicated by 150Y, after completing the basic transistor configuration. On the basis of the spacer element 165, the drain and source extension regions 152E are formed by ion implantation, possibly in combination with the incorporation of a counter-doping species in order to locally increase the well dopant concentration in the active region 102A, the basic dopant profile of which may have been adjusted prior to forming the gate electrode structures 160. Next, the spacer 166 may be formed, for instance, by depositing a silicon nitride material and patterning the same followed by a further implantation process in order to incorporate the dopant species for the deep drain and source areas 152D. It should be appreciated that the spacers 166 are provided so as to comply with the requirements for implementing a desired complex lateral and vertical dopant profile. The final dopant profile may then be established during one or more anneal processes, thereby also activating the dopant species and re-crystallizing implantation-induced damage. In some approaches, the width of the spacer elements 166 may be reduced by performing an appropriate etch process in order to obtain an increased lateral distance, as indicated by the distance 150X, in order to improve the conditions for the subsequent deposition of an interlayer dielectric material. In this case, also a certain loss of material in the active region 102A may be induced, thereby also contributing to the final degree of recessing 150Y. Thereafter, well-established silicidation techniques are applied in order to form the materials 153 and 163, wherein typically, at any appropriate manufacturing stage, the hard mask material is removed from above the electrode material 162, for instance upon reducing the width of the spacer 166 and the like.
FIG. 1b schematically illustrates the device 100 in a further advanced manufacturing stage. As illustrated, a first dielectric material 121 of a contact level 120 is formed above the active region 102A and the gate electrode structures 160. As explained above, frequently, the material 121 is provided in the form of a highly stressed dielectric material, such as a silicon nitride material, which is deposited on the basis of plasma enhanced chemical vapor deposition (CVD) techniques in which process parameters are adjusted such that a desired high internal stress is obtained. For example, when the transistors 150A, 150B are P-channel transistors, the material 121 is formed so as to have a high internal compressive stress. The deposition of the material 121, on the one hand, can provide a moderately thick layer with a high internal stress level in order to enhance performance of the transistors 150A, 150B, thereby requiring specific process parameters which, however, may not provide the required gap filling capabilities so as to completely fill the space between the gate electrode structures 160. Consequently, for densely packed device areas, even the reduction in width of the spacer 166 for obtaining the distance 150X may thus result in a void 121V positioned between the gate electrode structures 160. The void 121V may, however, result in device failures during the further processing, for instance upon forming a further interlayer dielectric material 122 and patterning the same so as to form contact openings 123 therein. In this case, the opening 123 may connect to the void 121V, which, however, may extend along a width direction, i.e., along a direction perpendicular to the drawing plane of FIG. 1b, so that, upon filling the contact opening 123, conductive material may be deposited in the void 121V, thereby forming a buried “tungsten channel” which may short adjacent contact elements, thereby causing significant yield loss.
As a consequence, the process strategy described above may cause significant yield loss in a final stage of forming the transistors 150A, 150B, while also the pronounced recessing 150Y may contribute to reduced transistor performance.
In view of the situation described above, the present disclosure relates to manufacturing techniques and semiconductor devices in which semiconductor devices, including field effect transistors formed with critical dimensions of 40 nm and less, may be provided, while avoiding or at least reducing the effects of one or more of the problems identified above.